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CYIH1SM1000AA-HHCS
Detailed Specification - ICD
1. Introduction
1.1 Scope
This version of the ICD is the version generated after qualification campaign closure. This specification details the ratings, physical, geometrical, electrical and electro-optical characteristics, test- and inspection-data for the High Accuracy Star Tracker (HAS) Version 2 CMOS Active Pixel image Sensor (CMOS APS). The device described in this document is protected by US patent 6,225,670 and others.
1.7 Handling Precautions
The component is susceptible to damage by electro-static discharge. Therefore, suitable precautions shall be employed for protection during all phases of manufacture, testing, packaging, shipment and any handling. The following guidelines are applicable:

Always manipulate the devices in an ESD controlled environment. Always store the devices in a shielded environment that protects against ESD damage (at least a non-ESD generating tray and a metal bag). Always wear a wrist strap when handling the devices and use ESD safe gloves. The HAS2 is classified as class 1A (JEDEC classification [AD03]) device for ESD sensitivity.
1.2 Component Type Variants
A summary of the type variants of the basic CMOS image sensor is given in Table 1 on page 8. The complete list of detailed specifications for each type variant is given in Table 3 on page 9 for each type separately. All specifications in Table 3 on page 9 are given at 25 3C, under nominal clocking and bias conditions. Exceptions are noted in the 'remarks' field.

1.8 Storage Information
The components must be stored in a dust-free and temperature-, humidity and ESD controlled environment.

1.3 Maximum Rating
The maximum ratings which shall not be exceeded at any time during use or storage are as scheduled in Table 2 on page 9.
Devices must always be stored in special ESD-safe trays such that the glass window is never touched. The trays are closed with EDS-safe rubber bands. The trays are sealed in an ESD-safe conductive foil in clean room conditions. For transport and storage outside a clean room the trays are packed in a second ESD-save bag that is sealed in clean room.
1.4 Physical Dimensions and Geometrical Information
The physical dimensions of the assembled component are shown in Figure 2 on page 25. The geometrical information in Figure 4 on page 26 describes the position of the die in the package.
1.9 Procurement Requirements
The HAS2 image sensor can be procured at Cypress Semiconductor or its distributors, using the following references:

1.5 Pin Assignment
Figure 6 on page 27 contains the pin assignment. The figure contains a schematic drawing and a pin list. A detailed functional description of each pin can be found in "Pin List" on page 39.
Flight sensors: CYIH1SM1000AA-HHCS. Engineering sensors: CYIH1SM1000AA-HHCES.
1.6 Soldering Instructions
Soldering is restricted to manual soldering only. No wave or reflow soldering is allowed. For the manual soldering, following restrictions are applicable:

The HAS sensor is subject to the standard European export regulations for dual use products. A Certificate of Conformance will be issued upon request at no additional charge. The CoC will refer to this Detailed Specification. Additional screening tests can be done upon request at additional cost. The following data is by default delivered with FM sensors:

Solder 1 pin on each of the 4 sides of the sensor. Cool down period of min. 1 minute before soldering another pin on each of the 4 sides. Repeat soldering of 1 pin on each side, including a 1 minute cool down period.
Sensor calibration data Temperature calibration data Certificate of Conformance to this detailed specification Visual inspection report Bad pixel map
Cypress Semiconductor Corporation Document Number: 001-54123 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 18, 2009
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2. Ordering Information
Marketing Part Number CYIH1SM1000AA-HHCS CYIH1SM1000AA-HHCES Description Space qualified (mono version) Standard Market (mono version) Package 84 pin JLCC 84 pin JLCC Production In production Nov-09
3. Applicable Documents
The following documents form part of this specification and shall be read in conjunction with it: Nr. AD01 AD02 AD03 AD04 AD05 AD06 Reference ESCC Generic Specification 9020 Cypress 001-06225[1] JESD22-A114-B APS2-FVD-06-003 Cypress 001-49283 Cypress 001-49280 Title Charge Coupled Devices, Silicon, Photosensitive Electro-optical test methods for CMOS image sensors Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) Process Identification Document for HAS2 Visual Inspection for FM devices HAS2 FM Screening Issue 2 Draft F E B 2 1 2 October, 2008 June, 2000 February, 2008 January, 2008 June, 2009 Date
4. Acronyms Used
For the purpose of this specification, the terms, definitions, abbreviations, symbols, and units specified in ESCC basic Specification 21300 shall apply. In addition, the following table contains terms that are specific to CMOS image sensors and are not listed in ESCC21300 Abbreviation ADC APS CDS DNL DR DSNU EPPL ESD FPN HAS INL MTF NDR PRNU TBC TBD RGA Description Analog to Digital Convertor Active Pixel Sensor Correlated Double Sampling Differential Non Linearity Destructive Readout Dark Signal Non Uniformity European Preferred Parts List Electro-Static Discharge Fixed Pattern Noise High Accuracy Startracker Integral Non Linearity Modulated Transfer Function Non Destructive Readout Pixel Response Non Uniformity To be Confirmed To be Defined Residual Gas Analysis
Note 1. This specification will be superseded by the ESCC basic specification 25000 which is currently under development. The current reference is an internal Cypress procedure which is a confidential document.
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The following formulas are applicable to convert % Vsat and mV/s into e- and e-/s:
tions and the tolerances as indicated in Figure 2 on page 25 and Figure 3 on page 26. 5.2.3 Weight The maximum weight of the components specified herein shall be as specified in Table 3 on page 9 - Mechanical Specifications, item 2.
FPN [e-] =
FPN [%Vsat ] *Vsat conversion _ gain
Dark _ signal[e - / s ] =
Dark _ signal[V / s ] conversion _ gain
5.3 Materials and Finishes
The materials and finishes shall be as specified herein. Where a definite material is not specified, a material which will enable the components specified herein to meet the performance requirements of this specification shall be used. 5.3.1 Case The case shall be hermetically sealed and have a ceramic body and a glass window. Type Material Thermal expansion coefficient Hermeticity Thermal resistance (Junction to case) 5.3.2 Lead material and finish Lead material 1e Finish 2nd Finish 5.3.3 Window The window material is a BK7G18 glass lid with anti-reflective coating applied on both sides. The optical quality of the glass shall have the following specification: See Table 3 on page 9 - glass window specification The anti reflective coating shall have a reflection coefficient < 1.3% absolute and < 0.8% on average, over a bandwidth from 440 nm to 1100 nm. KOVAR Nickel, min 2 m Gold, min 1.5 m JLCC-84 Black Alumina BA-914 7.6 x 10-6 /K < 5*10-7 atms. cm3/s 3.633 C/W
DSNU [%Vsat ] *Vsat DSNU [e-] = conversion _ gain
Other definitions:
Ana log Range ADC Re solution Conversion Gain ADC Quantization Noise = ADC Re solution

Conversion gain for HAS: 14.8 V/eDefinition for Local measurements: 32 x 32 pixels Definition for Global measurements: Full pixel array
5. Detailed Information
5.1 Deviations from Generic Specification
Lot acceptance and screening are based on ESCC 9020 issue 2 draft F. section 5.9 on page 5 of this specification describes the lot acceptance and screening.
5.2 Mechanical Requirements
5.2.1 Dimension Check The dimensions of the components specified herein shall be checked. They shall comply with the specifications and the tolerances as indicated in Figure 2 on page 25. 5.2.2 Geometrical Characteristics The geometrical characteristics of the components specified herein shall be checked. They shall comply with the specifica-
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5.4 Marking
5.4.1 General The marking Shall consist of a lead identification and traceability information. 5.4.2 Lead Identification An index to pin 1 shall be located on the top of the package in the position defined in Figure 2 on page 25. The pin numbering is counter clock-wise, when looking at the top-side of the component. 5.4.3 Traceability Information Each component shall be marked such that complete traceability can be maintained. The component shall bear a number that is constituted as follows: Indication of type. To be replaced by detail specification number when this is allocated.
HAS2 - FM
Type variant Serial number Production date (YYMMDD)
000001 061006
5.5 Electrical and Electro-optical Measurements
5.5.1 Electrical and Electro-optical Measurements at Reference Temperature The parameters to be measured to verify the electrical and electro-optical specifications are scheduled in Table 4 on page 14 and Table 13 on page 24. Unless otherwise specified, the measurements shall be performed at a environmental temperature of 223C. For all measurements the nominal power supply, bias and clocking conditions apply. The nominal power supply and bias conditions are given in Table 14 on page 24, the timing diagrams in Figure 35 on page 51 and Figure 37 on page 53. Remark: The given bias and power supply settings imply that the devices are measured in "soft- reset" condition. 5.5.2 Electrical and Electro-optical measurements at High and Low Temperature The parameters to be measured to verify the electrical and electro-optical specifications are scheduled in Table 5 on page 15 and Table 6 on page 16. Unless otherwise specified, the measurements shall be performed at -40 (-5 +0) C and at +85 (+5 -0) C. 5.5.3 Circuits for Electrical and Electro-optical Measurements Circuits for performing the electro-optical tests in Table 4 on page 14 and Table 13 on page 24 are shown in Figure 48 on page 63 to Figure 51 on page 63.
5.6 Burn-in Test
5.6.1 Parameter Drift Values The parameter drift values for power burn-in are specified in Table 7 on page 18 of this specification. Unless otherwise specified the measurements shall be conducted at a environmental temperature of 223C and under nominal power supply, bias and timing conditions. The parameter drift values shall not be exceeded. In addition to these drift value requirements, also the limit values of any parameter - as indicated in Table 4 on page 14 - shall not be exceeded. Conditions for high temperature reverse bias burn-in Not Applicable 5.6.2 Conditions for Power Burn-in The conditions for power burn-in shall be as specified in Table 10 on page 21 of this specification 5.6.3 Electrical Circuits for High Temperature Reverse Bias Burn-in Not Applicable 5.6.4 Electrical Circuits for Power Burn-in Circuits to perform the power burn-in test are shown in Figure 48 on page 63 and next ones of this specification.
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5.7 Environmental and Endurance Tests
5.7.1 Electrical and Electro-optical Measurements on Completion of Environmental Test The parameters to be measured on completion of environmental tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at a environmental temperature of 223C. Measurements of dark current must be performed at 221C and the actual environmental temperature must be reported with the test results. 5.7.2 Electrical and Electro-optical Measurements At Intermediate Point During Endurance Test The parameters to be measured at intermediate points during endurance test of environmental tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at an environmental temperature of 223C 5.7.3 Electrical and electro-optical measurements on Completion of Endurance Test The parameters to be measured on completion of endurance tests are scheduled in Table 11 on page 21. Unless otherwise stated, the measurements shall be performed at a environmental temperature of 223C 5.7.4 Conditions for Operating Life Test The conditions for operating life tests shall be as specified in Table 10 on page 21 of this specification. 5.7.5 Electrical Circuits for Operating Life Test Circuits for performing the operating life test are shown in Figure 48 on page 63 and next ones of this specification. 5.7.6 Conditions for High Temperature Storage Test The temperature to be applied shall be the maximum storage temperature specified in Table 2 on page 9 of this specification. Test Wafer processing data review SEM Total dose test Endurance test Test method PID ESCC 21400 ESCC 22900 MIL-STD-883 Method 1005
5.8 Total Dose Radiation Test
5.8.1 Application The total dose radiation test shall be performed in accordance with the requirements of ESCC Basic specification 22900. 5.8.2 Parameter Drift Values The allowable parameter drift values after total dose irradiation are listed in Table 8 on page 19. The parameters shown are valid after a total dose of 42KRad and 168h/100C annealing. 5.8.3 Bias conditions Continuous bias shall be applied during irradiation testing as shown in Figure 48 on page 63 and next ones of this specification. 5.8.4 Electrical and Electro-optical Measurements The parameters to be measured, prior to, during and on completion of the irradiation are listed in Table 13 on page 24 of this specification. Only devices that meet the specification in Table 4 on page 14 of this specification shall be included in the test samples.
5.9 Lot Acceptance and Screening
This paragraph describes the Lot Acceptance Testing (LAT) and screening on the HAS FM devices. All tests on device level have to be performed on screened devices (see Table 5.9.6 on page 7). 5.9.1 Wafer Lot Acceptance This is the acceptance of the silicon wafer lot. This has to be done on every wafer lot that will be used for the assembly of flight models.
Number of devices NA 4 naked dies 3 devices 6 devices
Test condition NA NA 42 krad : 1krad/h 2000h at +125 C
Test location CY Test house ESTEC by CY Test House
Before and after total dose test and endurance test:
5.9.2 Glass Lot Acceptance Transmission and reflectance curves that are delievered with each lot shall be compared with the specifications in Table , "Glass Lid Specification," on page 10 3 glass lid shall be chosen randomly from the lot and will be measured in detail. All obtained results will be compared with Figure 5 on page 27.
Electrical measurements before and after at high, low and room temperature. Conform Table 4 on page 14 and Table 5 on page 15,Table 6 on page 16 of this specification. Visual inspection before and after Detailed electro optical measurements before and after

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5.9.3 Package lot acceptance 5 packages shall be chosen randomly from the lot and will be measured in detail. All obtained results will be compared with Figure 2 on page 25. 5.9.4 Assembly Lot Acceptance Test Special assembly house in process control Bond strength test Assembly House Geometrical data review Solder ability Terminal strength Marking permanence Geometrical measurements Temperature cycling MIL-STD-883 method 2011 Review MIL-STD883, method 2003 MIL-STD 883, method 2004 ESCC 24800 PID MIL-STD 883, method 1010 Test method
A solderability test is covered in the assembly lot acceptance tests (Table 5.9.4).
Number of devices
Test condition
Test location Assembly House
2 All
D
Assembly House CY
D 3
Test House
All Condition B 50 cycles -55C/+125C 240h at 85C/85% N/A 4 All wires
CY Test House
5 Moisture resistance DPA: Die shear test Bond pull test MIL-STD-883 method 2019 MIL-STD-883 method 2011 JEDEC Std. Method A101-B
Test House Test House Test House
Before and after the following tests are done:

Electrical measurements conform Table 4 on page 14 of this specification Detailed visual inspection
Fine leak test + Gross leak test Fine- and gross-leak tests shall be performed using the following methods: Fine Leak test: MIL-STD-883, Test Method 1014, Condition A Gross Leak test: MIL-STD-883, Test Method 1014, Condition C The required leak rate for fine leak testing is 5*10-7 atms. cm3/s
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5.9.5 Periodic Testing Test Mechanical Shock Test method MIL-STD 883, method 2002 Number of devices 2 Test condition B - 5 shocks, 1500g - 0,5ms - 1/2 sine, 6 axes A - 4 cycles, 20g 80 to 2000 Hz, 0,06 inch 20 to 80 Hz, 3 axes N/A 2 All wires Test location Test House
Mechanical Vibration
MIL-STD 883, method 2007
2
Test House
DPA:
Die shear test Bond pull test
MIL-STD-883 method 2019 MIL-STD-883 method 2011
Test House Test House
Periodic testing is required every 2 years. Before and after the following tests are done:

Electrical measurements conform Table 4 on page 14. Detailed visual inspection Fine leak test + Gross leak test
Fine- and gross-leak tests shall be performed using the following methods: Fine Leak test: MIL-STD-883, Test Method 1014, Condition A Gross Leak test: MIL-STD-883, Test Method 1014, Condition C The required leak rate for fine leak testing is 5*10 7 atms. cm3/s 5.9.6 Screening Nr. 1 Test HCRT Electrical measurements Visual inspection Die placement measurements XRAY Stabilization bake Fine leak test Gross leak test Temperature cycling Biased Burn-in Mobile Particle Detection Fine leak test Gross leak test HCRT Electrical measurements Final Visual Inspection Test method 001-53958 Number of devices All Test condition HT +85C LT -40C RT +25C Test location CY
2 3 4 5 6 7 8 9 10 11 12 13
001-49283 + ICD Cypress internal proc. ESCC 20900 MIL-STD-883 method 1008 MIL-STD-883 method 1014 MIL-STD-883 method 1014 MIL-STD-883 method 1010 ICD MIL-STD-883 method 2020 MIL-STD-883 method 1014 MIL-STD-883 method 1014 001-53958
All All All All All All All All All All All All 48h at 125C A C B - 10 cycles -55C +125C 240h at +125C. A A C HT +85C LT -40C RT +25C
CY CY Test House Test House Test House Test House Test House CY Test House Test House Test House CY
14
001-49283 + ICD
All
CY
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6. Tables and Figures
6.1 Specification Tables
Table 1. Type Variant Summary HAS2 Type Variants Dead pixels Bright pixels in FPN image Bad pixels in PRNU image Bad columns Bad rows Bright pixel clusters: 2 adjacent bright pixels 4 or more adjacent bright pixels DSNU defects @ 22 dec BOL DSNU defects @ 22 dec EOL Particle Contamination Fixed particles outside focal plane Mobile particles > 20um Fixed particles on focal plane > 20um Mobile particles > 10um and < 20um Fixed particles on focal plane > 10um and < 20um Particles < 10um Wafer lot acceptance (section 5.9.1 on page 5) Glass lot acceptance (section 5.9.2 on page 5) Assembly lot acceptance (Table 5.9.4 on page 6) Periodic testing (Table 5.9.5 on page 7) Screening (Table 5.9.6 on page 7) Calibration data Visual Inspection + particle mapping N/A NO NO NO NO NO Optional Optional N/A YES YES YES YES YES YES YES N/A 0 0 20 N/A 0 0 10 25 10 1200 1500 2 0 1000 1250 Engineering samples (HHCES) 100 50 150 5 5 Flight model samples (HHCS) 20 20 50 0 0
Optical Quality (See "Optical quality - Definitions" on page 70.)
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Table 2. Maximum Ratings No 1 2 Characteristic Any supply voltage except VDD_RES Supply voltage at VDD_RES Min -0.5 -0.5 Typ 3.3 3.3 Max +7.0 +5.0 Unit V V 3.3V for normal operation; up to 5V for increased full well capacity. Remarks
3 4
Voltage on any input terminal Soldering temperature
-0.5 NA
3.3 NA
Vdd + 0.5 260
V C Hand soldering only; See section 1.6 on page 1 for soldering instructions
5 6
Operating temperature Storage temperature
-40 -55
NA NA
+85 +125
C C
Table 3. Detailed Specification All Type Variants General Characteristics No 1 2 3 Characteristic Image sensor format Pixel size ADC resolution Min N/A N/A N/A Typ 1024x 1024 18 12 Max N/A N/A N/A Unit pixels Remarks
m
bit 10 bit accuracy at 5 Msamples / sec
Silicon Particle Contamination Specification No 1 Characteristic Optical quality: Particle max size Min N/A Typ N/A Max 20 Unit um Remarks See "Type Variant Summary" on page 8
Mechanical Specifications No 1a Characteristic Flatness of image area Min NA Typ 7.4 Max NA Unit Remarks Peak-to-peak at 25 3 C Specified by the foundry over an entire 8" wafer Towards ceramic package Package + epoxy + glass lid Die in center of cavity Die in center of cavity
m m
g mm mm mm mm mm
1b 2 3 4a 4b 5 6 7 8
Flatness of glass lid Mass Total thickness Die position, X offset Die position, Y offset Die position, parallelism vs window Die position, parallelism vs backside Die position, Y tilt Die position, X tilt Die - window distance
NA 7.7 3.2 NA NA -0.1 0.1 -0.1 -0.1 0.25
90 7.85 3.3 NA NA 0 0 0 0 0.3
150 8.0 3.4 0.1 0.1 0.1 0.1 0.1 0.1 0.35
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Glass Lid Specification No 1a 1b 2a 2b 3 XY size Thickness Spectral range for optical coating of window Reflection coefficient for window Optical quality: Scratch max width Scratch max number Dig max size Dig max number Characteristic Min 26.7 x 26.7 1.4 440 NA N/A Typ 26.8 x 26.8 1.5 NA <0.8 N/A 10 5 60 25 Max 26.9 x 26.9 1.6 1100 <1.3 Unit mm mm nm % Over bandwidth indicated in 2a Remarks
m
Environmental Specification No 1 2 Characteristic Operating temperature Storage temperature Min -40 -55 Typ NA NA Max +85 +125 Unit C C Lower storage temperatures (to -80 deg C ) have been tested and the device survives but this is not a fully qualified temperature. Tested for functionality up to 300krad, 42 krad is guaranteed Equivalent LET value Remarks
3
Sensor total dose radiation tolerance
N/A
42
N/A
krad (Si) MeV cm3 mg-1
4
sensor SEL threshold with ADC enabled
NA
NA
>110
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Electrical Specification No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational: analog + digital Power supply current to image core, operational Input impedance digital input Input impedance ADC input Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC ladder network resistance ADC Differential non linearity ADC Integral non linearity ADC set-up time ADC hold time ADC delay time ADC latency ADC ideal input range Saturation voltage output swing Output range Min 16 35 17 14 3 3 2.2 NA 1.9 3.8 7.2 0.86 1.30 0.43 0.80 NA NA NA 5 10 NA NA 0.85 1.20 0.8 Typ 18.5 37 19 15.5 NA NA 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 1.8 7 8 NA NA NA 6.5 NA 1.49 NA Max 21 40 21 17 NA NA 2.6 NA 2.3 4.4 8.2 1.0 1.40 0.6 1.0 NA 11 18 NA NA 20 NA 2.0 NA 2.1 Unit mA mA mA mA M M V V V V V k lsb lsb ns ns ns V V V Cycles of CLK_ADC VLOW_ADC to VHIGH_ADC VDD_RES=3.3V Measured with PGA in unity gain, offset=0.8V, low is dark, high is bright. Measured within 1% Measured within 5% Measured with VDD_RES=3.3V Measured between 500 nm and 650 nm. Refer to section 6.3.1 for complete curve. Measured average over 400-900nm. Page 11 of 71 Analog_in stable to CLK_ADC rising Analog_in stable after CLK_ADC rising edge Typical value Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate Measured ADC at 5MHz sampling rate Measured Remarks
26 27 28 29
Linear range of pixel signal swing Linear range Full well charge Quantum efficiency x Fillfactor
40 60 90 NA
50 0.75 82 100 45
NA NA NA NA
keV keke%
30
Spectral response
NA
33.3
NA
%
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Electrical Specification No 31 32 33a 33b 33c 34a 34b 34c 35 36a 36b 36c 37a 37b 37c 37d 37e 38 Characteristic Charge to voltage conversion factor Charge to voltage conversion factor Temporal noise (Soft Reset) Temporal noise (Hard Reset) Temporal noise (HTS Reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantization noise Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (NDR, Soft reset) Local Column fixed pattern noise standard deviation (NDR, Soft reset) Average dark signal Min NA 13 NA N/A NA NA NA NA NA NA NA NA NA NA NA 14 14 NA Typ 16.9 14.8 55 75 65 75 75 70 7 110 70 95 115 90 110 15 15 190 Max NA 15.6 95 125 110 100 100 100 NA 160 140 140 180 140 180 18 18 400 Unit Remarks At pixel Measured at output SIGNAL_OUT, unity gain Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC
V/eV/eeeeeeeeeeeeeeeee-/s
With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With NDR/CDS and external ADC With NDR/CDS and external ADC At 25 2 C die temp, BOL see "Dark Current vs Temperature Model" on page 33 At 25 2 C die temp, EOL (25 krad) Sensor temperature increase for doubled average dark current. At 25 2 C die temp, BOL 96% of BOL average At 25 2 C die temp, BOL 96% of BOL average Of average response Of average response At Nyquist measured At Nyquist measured
39 40
Average dark signal Dark signal temperature dependency
NA 5
5550 5.8
8730 8
e-/s C
41 42 43 44 45 46
Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation MTF X direction MTF Y direction
NA N/A NA NA NA NA
260 275 0.8 1.8 0.35 0.35
400 500 1.0 5 NA NA
e-/s e-/s % % NA -
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Electrical Specification No 47 48 49 50 51 52 53 54 55 56a 56b 56c Characteristic Pixel to pixel crosstalk X direction Pixel to pixel crosstalk Y direction Anti-blooming capability Pixel rate Temperature sensor transfer curve Temperature sensor output signal range, Min to Max (typical) Temperature sensor linearity Temperature sensor transfer curve Temperature sensor output signal range, Min to Max (typical) Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Min NA NA 200 NA NA 800 NA NA 800 NA NA NA Typ 9.8 9.8 1000 5 -4.64 NA 3 -4.64 NA 0.54 -0.2 -0.15 Max NA NA NA 10 NA 1700 NA NA 1700 NA NA NA MHz mV/C mV mV mV/C NA BOL BOL BOL EOL EOL Soft reset Hard reset HTS reset Unit % % Remarks Of total source signal - see section 6.3.6 for 2-D plot Of total Source signal - see section 6.3.6 for 2-D plot Typical
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Table 4. Electrical and Electro-optical Measurements at Room Temperature Electrical and Electro-optical Measurements at Room Temperature 22C No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22a 22b 22c 23a 23b 23c 24 25a 25b 25c Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Input impedance digital input Input impedance ADC input Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantization noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Min 16 35 17 14 3 3 NA NA 2.2 NA 1.9 3.8 7.2 0.86 1.30 0.43 0.80 N/A N/A 1.20 0.8 NA NA NA NA NA NA NA N/A NA NA Typ 18.5 37 19 15.5 NA NA NA NA 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 7 8 1.49 NA 55 75 65 75 75 70 7 70 110 95 Max 21 40 21 17 NA NA 400 1 2.6 NA 2.3 4.4 8.2 1.0 1.40 0.6 1.0 11 18 NA 2.1 95 125 110 100 100 100 NA 140 160 140 Unit mA mA mA mA M M W k V V V V V lsb lsb V V eeeeeeeeeeWith DR/DS With DR/DS With DR/DS VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at Room Temperature 22C No. 26a 26b 26c 27 28 29 30 31 32a 32b 32c Characteristic Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Min NA NA NA NA NA NA NA NA NA NA NA Typ 90 115 110 190 260 275 0.8 1.8 0.54 -0.2 -0.15 Max 140 180 180 400 400 500 1.0 5 NA NA NA Unit eeee-/s e-/s e-/s % % Remarks With DR/DS With DR/DS With DR/DS At 25 2 C die temp At 25 2 C At 25 2 C Of average response Of average response
Table 5. Electrical and Electro-optical measurements at High Temperature Electrical and Electro-optical Measurements at High Temperature +85C No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Input impedance digital input Input impedance ADC input Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Min 17 35 17 14 3 3 NA NA 2.2 NA 1.9 3.7 7.0 0.89 1.30 0.43 0.83 NA NA Typ 20 38 19 15.5 NA NA NA NA 2.45 1 2.1 4.0 7.5 0.94 1.36 0.53 0.93 8 10 Max 23 41 21 17 NA NA 400 1 2.6 NA 2.3 4.3 8.0 1.0 1.42 0.63 1.03 11 18 Unit mA mA mA mA M M W k V V V V V lsb lsb Page 15 of 71 Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at High Temperature +85C No 20 21 22a 22b 22c 23a 23b 23c 24 25a 25b 25c 26a 26b 26c 27 28 29 30 31 32a 32b 32c Characteristic Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantization noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Min 1.20 0.8 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Typ 1.52 NA 66 85 73 200 170 65 7 82 95 100 80 97 115 41000 2800 3100 0.74 1.7 -0.13 -0.09 -0.12 Max NA 2.1 110 125 110 400 300 125 NA 160 160 160 140 160 300 60000 4000 4500 1.0 5 NA NA NA Unit V V eeeeeeeeeeeeee-/s e-/s e-/s % % Of average response Of average response Soft reset Hard reset HTS reset With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS At +85 2 C die temp Remarks VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. DR/DS DR/DS DR/DS
Table 6. Electrical and Electro-optical measurements at Low Temperature Electrical and Electro-optical Measurements at Low Temperature -40C No 1 2 3 4 5 6 7 Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Input impedance digital input Input impedance ADC input Output impedance digital outputs Min 16 35 17 14 3 3 NA Typ 18 37 19 15.5 NA NA NA Max 21 40 21 17 NA NA 400 Unit mA mA mA mA M M W Page 16 of 71 ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at Low Temperature -40C No 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22a 22b 22c 23a 23b 23c 24 25a 25b 25c 26a 26b 26c 27 28 29 30 31 Characteristic Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantization noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Min NA 2.2 NA 1.9 3.8 7.2 0.86 1.30 0.43 0.80 N/A N/A 1.20 0.8 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Typ NA 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 7 11 1.49 NA 59 77 70 80 80 75 7 70 90 100 70 95 120 3.3 6 8 0.8 1.8 Max 1 2.6 NA 2.3 4.4 8.2 1.0 1.40 0.6 1.0 11 18 NA 2.1 100 125 125 125 125 125 NA 140 140 160 140 140 180 10 20 30 1.0 5 Unit k V V V V V lsb lsb V V eeeeeeeeeeeeee-/s e-/s e-/s % % Of average response measured Of average response measured Page 17 of 71 With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. DR/DS DR/DS DR/DS Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value Remarks
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Electrical and Electro-optical Measurements at Low Temperature -40C No 32a 32b 32c Image lag Image lag Image lag Characteristic Min NA NA NA Typ 0.6 0.2 -1.2 Max NA NA NA Unit Soft reset Hard reset HTS reset Remarks
Table 7. Parameter Drift Values for Burn In Electrical and Electro-optical Measurements at Room Temperature +22C No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20a 20b 20c 21a 21b 21c 22 23a Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantisation noise Local fixed pattern noise standard deviation (Soft reset) Typical Value 18.5 37 19 15.5 NA NA 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 7 8 1.49 NA 55 75 65 75 75 70 7 70 Max Drift 2 3 2 2 20 20 0.3 N/A 0.2 0.4 0.6 0.1 0.1 0.1 0.1 2 2 0.2 0.2 +15 +15 +15 +15 +15 +15 NA +15 Unit mA mA mA mA W W V V V V V lsb lsb V V eeeeeeeeWith DR/DS VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. Dark noise, with DR/DS, internal ADC DARK noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at Room Temperature +22C No 23b 23c 24a 24b 24c 25 26 27 28 29 30a 30b 30c Characteristic Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Typical Value 110 95 90 115 110 190 260 275 0.8 1.8 0.54 -0.2 -0.15 Max Drift +15 +30 +15 +15 +50 +50 +50 +50 +0.1 +0.3 NA NA NA Unit eeeeee-/s e-/s e-/s % % Remarks With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS At 25 2 C die temp At 25 2 C At 25 2 C Of average response Of average response
Table 8. Parameter Drift Values for Radiation Testing Electrical and Electro-optical Measurements at Room Temperature +22C No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 Typical Value 18.5 37 19 15.5 N/A N/A 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 Max Drift 2 3 2 2 20 20 0.2 N/A 0.2 0.3 0.5 0.1 0.1 0.1 0.1 Unit mA mA mA mA W W V V V V V Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at Room Temperature +22C No 16 17 18 19 20a 20b 20c 21a 21b 21c 22 23a 23b 23c 24a 24b 24c 25 26 27 28 29 30a 30b 30c Characteristic ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantisation noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Typical Value 7 8 1.49 N/A 55 75 65 75 75 70 7 70 110 95 90 115 110 190 260 275 0.8 1.8 0.54 -0.2 -0.15 Max Drift 1 1 0.2 0.2 +30 +30 +30 +40 +40 +40 NA +200 +100 +100 +200 +100 +100 +6000 +1500 +1500 +0.1 +0.3 NA NA NA Unit lsb lsb V V eeeeeeeeeeeeee-/s e-/s e-/s % % With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS At 25 2 C die temp At 25 2 C At 25 2 C Of average response Of average response VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Remarks
Table 9. Conditions for High Temperature Reverse Bias Burn-in No Not applicable Characteristics Symbol Test condition Unit
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Table 10. Conditions for Power Burn-in and Operating Life Tests No 1 2 3 4 Characteristics Ambient temp All power supplies Bias conditions Clock frequency Symbol Tamb Vdd Test condition 125 3.3 See Figure 48 on page 63 and next ones 10 MHz Unit C V
Table 11. Electrical and Electro-optical Measurements on Completion of Environmental Tests and at Intermediate Points and on Completion of Endurance Testing Electrical and Electro-optical Measurements at Room Temperature +22C No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22a 22b 22c 23a 23b Characteristic Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Input impedance digital input Input impedance ADC input Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Min 16 35 17 14 3 3 NA NA 2.2 NA 1.9 3.8 7.2 0.86 1.30 0.43 0.80 NA NA 1.20 0.8 NA NA NA NA NA Typ 18.5 37 19 15.5 NA NA NA NA 2.45 1 2.1 4.1 7.7 0.93 1.35 0.51 0.90 7 8 1.49 NA 55 75 65 75 75 Max 21 40 21 17 NA NA 400 1 2.6 NA 2.3 4.4 8.2 1.0 1.40 0.6 1.0 11 18 N/A 2.1 95 125 110 100 100 Unit mA mA mA mA M M W k V V V V V lsb lsb V V eeeeePage 21 of 71 VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. DARK noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 Nominal 8 relative to setting 0 0 decodes to middle value ADC at 5MHz sampling rate measured at 5MHz Remarks
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Electrical and Electro-optical Measurements at Room Temperature +22C No 23c 24 25a 25b 25c 26a 26b 26c 27 28 29 30 31 32a 32b 32c Characteristic Temporal noise (NDR HTS reset) ADC quantisation noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Min NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Typ 70 7 70 110 95 90 115 110 190 260 275 0.8 1.8 0.54 -0.2 -0.15 Max 100 NA 140 160 140 140 180 180 400 400 500 1.0 5 NA NA NA Unit eeeeeeeee-/s e-/s e-/s % % With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS At 25 2 C die temp At 25 2 C At 25 2 C Of average response Of average response Remarks
Table 12. Electrical and Electro-optical Measurements during and on Completion of Total-dose Irradiation Testing (50krad) Electrical and Electro-optical Measurements at Room Temperature +22C No 1 2 3 4 5 6 7 8 9 10 Characteristic Symbol Total power supply current stand-by Total power supply current, operational Power supply current to ADC, operational Power supply current to image core, operational Output impedance digital outputs Output impedance analogue output Output amplifier voltage range Output amplifier gain setting 0 Output amplifier gain setting 1 Output amplifier gain setting 2 Min 16 35 17 14 NA NA 2.2 NA 1.9 3.8 Typ 18.5 37 19 15.5 NA NA 2.45 1 2.1 4.1 Max 21 40 21 17 400 1 2.6 NA 2.3 4.4 Unit mA mA mA mA W k V Nominal 1 measured reference Nominal 2 relative to setting 0 Nominal 4 relative to setting 0 ADC at 5MHz sampling rate ADC at 5MHz sampling rate Remarks
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Electrical and Electro-optical Measurements at Room Temperature +22C No 11 12 13 14 15 16 17 18 19 20 21 22a 22b 22c 23a 23b 23c 24 25a 25b 25c 26a 26b 26c 27 28 29 30 31 32a Characteristic Symbol Output amplifier gain setting 3 Output amplifier offset setting 0 Output amplifier offset setting 31 Output amplifier offset setting 32 Output amplifier offset setting 63 ADC Differential non linearity ADC Integral non linearity Saturation voltage output swing Output range Temporal noise (Soft reset) Temporal noise (Hard reset) Temporal noise (HTS reset) Temporal noise (NDR Soft reset) Temporal noise (NDR Hard reset) Temporal noise (NDR HTS reset) ADC quantization noise Local fixed pattern noise standard deviation (Soft reset) Local fixed pattern noise standard deviation (Hard reset) Local fixed pattern noise standard deviation (HTS reset) Global fixed pattern noise standard deviation (Soft reset) Global fixed pattern noise standard deviation (Hard reset) Global fixed pattern noise standard deviation (HTS reset) Average dark signal Local dark signal non uniformity standard deviation Global dark signal non uniformity standard deviation Local photo response non uniformity, standard deviation Global photo response non uniformity, standard deviation Image lag (Soft reset) Image lag (Hard reset) Image lag (HTS reset) Min 7.2 0.86 1.30 0.43 0.80 N/A N/A 1.20 0.8 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA Typ 7.7 0.93 1.35 0.51 0.90 8 9 1.49 N/A 55 75 65 75 75 70 7 70 110 95 90 115 110 5550 260 275 0.8 1.8 0.54 -0.2 -0.15 Max 8.2 1.0 1.40 0.6 1.0 11 18 N/A 2.1 95 125 110 100 100 100 NA 350 160 200 350 180 200 8730 2000 2000 1.0 5 NA NA NA Unit V V V V lsb lsb V V eeeeeeeeeeeeee-/s e-/s e-/s % % With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS With DR/DS At 25 2 C die temp At 25 2 C At 25 2 C Of average response Of average response VDD_RES=3.3V PGA in unity gain, offset=0.8V, low is dark, high is bright. Dark noise, with DR/DS, internal AD Dark noise, with DR/DS, internal ADC Dark noise, with DR/DS, internal ADC Remarks Nominal 8 relative to setting 0 0 decodes to middle value
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Table 13. Electro-optical Measurements on the Optical Bench No 1 2 3 4 Characteristic Symbol Linear range of pixel signal swing Linear range Full well charge Quantum efficiency x Fillfactor Min 40 60 90 NA Typ 50 0.75 82 100 45 Max NA NA NA NA Unit keV keke% Remarks Measured within 1% Measured within 5% Measured VDD_RES=3.3V Measured between 500 nm and 650 nm. Refer to "Specification Figures" on page 25 for complete curve Measured average over 400-900nm. at pixel Measured at output SIGNAL_OUT, unity gain at Nyquist measured at Nyquist measured of total source signal - see "Specification Figures" on page 25 for 2-D plot of total source signal - see "Specification Figures" on page 25 for 2-D plot predicted value
5 6 7 8 9 10
Spectral Response Charge to voltage conversion factor Charge to voltage conversion factor MTF X direction MTF Y direction Pixel to pixel crosstalk X direction
NA NA 13 NA NA NA
33.3 16.9 14.8 0.35 0.35 9.8
15.6 NA NA NA
%
V/eV/e%
11
Pixel to pixel crosstalk Y direction
NA
9.8
NA
%
12
Anti-blooming capability
NA
1000
NA
Ke-
Table 14. Typical Power Supply Settings and Sensor Settings Power Supply Settings ADC_VLOW ADC_VHIGH V_ADC_DIGITAL V_ADC_ANALOG VDDD VDDA VRES VPIX Sensor Settings Read Out Modes Integration Time Gain Setting Offset Setting X Clock Period Destructive - Non Destructive 195 us Unity 0 100ns 0.85V 2.0V 3.3V 3.3V 3.3V 3.3V 3.3V for SR / 4.2V for HR 3.3V (for HTS switched to 0.75V)
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6.2 Specification Figures
Figure 1. 84L JLCC Package
001-07594**
Figure 2. Physical and Geometrical Package Drawings
001-07594**
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Figure 3. HAS2 Assembled Device Side View
Figure 4. Die Placement Dimensions
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Figure 5. Glass Lid Dimensions
Figure 6. Pin Assignment
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Figure 7. HAS2 Physical Layout
6.3 Typical data
6.3.1 Spectral Response Figure 8. Measured Spectral Response of HAS Rad-hard Pixel. Black Curve indicates Average Spectral Response
0.3 60 % 50 % 40 %
0.25 30 %
Spectral res ponse [A/W]
0.2
20 % 0.15
0.1 10 %
0.05
0 4 00
500
600
700
800
9 00
1000
Wavelength [nm]
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Figure 9. Average Measured Spectral Response of HAS Rad-hard Pixel Recalculated to QExFF
50 45 40 35 30 25 20 15 10 5 0 400 measured average curve smoothed trend
QE x FF [%]
500
600
700
800
900
1000
Wavelength [nm]
6.3.2 Photo-response Curve Figure 10. Pixel Response Curve: Photo-electrons versus Signal Voltage
1.6 pix pix pix pix 1 2 3 4
1.4
1.2
Output voltage [V]
1
0.8
0.6
0.4
0.2
0 0 20000 40000 60000 80000 100000 120000 140000
Number of electrons
Fit to the linear response curve with the same conversion gain (solid black line). The dashed lines indicate linear response curves with -5% and +5% conversion gain A detailed analysis is performed in the range < 4000 e-. The dashed lines corresponds to soft reset. The others to hard reset. Document Number: 001-54123 Rev. *A Page 29 of 71
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Figure 11. Pixel Response Curve < 4000e-
Figure 12. Measured Response Curves of Two Pixels on Two Devices at different Gain Setting
gain 4 (4.54)
2
gain 8 (8.55)
gain 2 (2.27)
1.5
Output voltage [V]
gain 1 (1)
1
0.5
0 0 20000 40000 60000 80000 100000 120000
Number of electrons [e-]
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Table 15. Overview of the Offset at different Gain Settings Device Gain setting 1 2 4 8 Offset offset_g1 offset_g2 offset_g4 offset_g8 1 [V] 0.86 0.93 1.02 1.18 6 [V] 0.85 0.91 0.99 1.14 Average [V] 0.86 0.92 1.00 1.16 Average Offset drift [mV] 0 65 149 303
6.3.3 Fixed Pattern Noise Figure 13 shows a log linear plot of the fixed pattern noise in destructive readout before and after radiation. Figure 13. Typical FPN Histogram in DR Before and After TID
FPN DR Histogram TID
1 00 00 0
BOL 4KRad T ID 13KRad T ID 20KRad T ID
10 00 0
41KRad T ID
1 00 0
# Pixels
10 0 10
1 1 00 15 0 2 00 25 0 300 3 50 40 0
2^12 [DN]
Figure 12 on page 30 shows a log linear plot of the fixed pattern noise in destructive readout before and after a 2000h life test which can be considered as EOL 41ehavior.
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Figure 14. Fpn Histogram in DR before and after 2000h Life Test
DR Histogram BOL - EOL
10 000 0
BOL EOL
1 000 0
100 0
# Pixels
10 0 10 1 200
2 20
24 0
26 0
280
3 00
3 20
34 0
2^12 [DN]
Figure 15 shows a log linear plot of the fixed pattern noise in non destructive readout before and after a 2000h life test which can be considered as EOL 42ehavior. Figure 15. FPN Histogram in NDR before and after 2000h Life test
NDR Reset Level Histogram BOL - EOL
1 00 00 0
BOL EOL
10 00 0
1 00 0
# Pixels
10 0 10
1 0 1 00 20 0 3 00 40 0 50 0 6 00 70 0 8 00 900 1 00 0
2^12 [DN]
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6.3.4 Dark Current vs Temperature Model Figure 16. Temperature Dependence of the Dark Current (in e/s) Measured on a Sample
1000000
100000
10000 Average Dark Current [e-/s]
y = 16.336e 2 R = 0.9995
0.1 08 2x
1000
100
10
Theoretical Curve
1 -60 -40 -20 0 20 40 60 80 100
0.1 Temperature [degC]
Following model is consistent with what has been measured for typical values:
DC
= DC0 2
T -T0 TDC ,d 1
+ a DC TID 2
T -T0 TDCNU ,d 1
T -T0 TDC ,d 2 T -T0 TDCNU ,d 2
DCNU
with
= DCNU 0 2
+ a DCNU TID 2
DC the dark current in e/s DC0 the dark current at 30 C and 0 krad = 300 e/s TID the total ionizing dose (in krad(Si)) T the temperature (in C) aDC the slope of the curve at 30 C = 325 e/s/krad(Si)
TDC,d1 = 5.8 C and TDC,d2 = 7.1 C
DCNU0 the dark current non-uniformity at 30 C and 0 krad = 230 e/s aDCNU the slope of the curve at 30 C = 33.6 e/s/krad(Si)
TDCNU,d1 = 9.5 C and TDCNU,d2 = 9.5 C
T0 = 30 C
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Following model is consistent with what has been measured for worst case values:
DC = DC0 2 DC = DC0 2 DCNU
T -T0 TDC , d 1, L
+ aDC TID 2 + aDC TID 2
T -T0 TDCNU ,d 1, L
T -T0 TDC , d 2 , L
for T < T0
T -T0 TDC , d1, H
T -T0 TDC ,d 2, H
for T > T0
T -T0 TDCNU ,d 2 ,L
= DCNU 0 2 = DCNU 0 2
+ aDCNU TID 2
for T < T0
DCNU
with
T -T0 TDCNU , d 1,H
+ aDCNU TID 2
T -T0 TDCNU , d 2, H
for T > T0
DC the dark current in e/s DC0 the dark current at 30 C and 0 krad = 550 e/s TID the total ionizing dose (in krad(Si)) T the temperature (in C) aDC the slope of the curve at 30 C = 480 e/s/krad(Si)
TDC,d1,L = 6.6 C and TDC,d2,L = 8 C for T < T0 TDC,d1,H = 5 C and TDC,d2,H = 6.5 C for T > T0
DCNU0 the dark current non-uniformity at 30 C and 0 krad = 400 e/s aDCNU the slope of the curve at 30 C = 45 e/s/krad(Si)
TDCNU,d1,L = 10.5 C and TDCNU,d2,L = 10.5 C for T < T0 TDCNU,d1,H = 8.5 C and TDCNU,d2,H = 8.5 C for T > T0
T0 = 30 C
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DCNU Distributions Figure 17 and Figure 18 show the distributions of the dark current in mV/s and e/s respectively for a number of devices and the average distribution. Figure 17. Dark Current Distribution (in mV/s) at 25 C Ambient Temperature
10000 ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average
1000
100
Relative frequency
10
1
0.1
0.01
0.001 0 20 40 60 80 100 120 140 160 180 200
Dark current [mV/s]
Figure 18. Dark Current Distribution (in e/s) at 25 C Ambient Temperature
10000 ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average
1000
100
Relative frequency
10
1
0.1
0.01
0.001 0 2000 4000 6000 8000 10000 12000
Dark current [e/s]
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Figure 19 and Figure 20 show the cumulative distributions of the dark current in mV/s and e/s respectively for a number of devices and the average cumulative distribution. Figure 19. Cumulative Dark Current Distribution (in mV/s) at 25 C Ambient Temperature
100 ext dev 1 ext dev 6 10 ext dev 10 int dev 1 int dev 6 int dev 10 average
Cumulative frequency
1
0.1
0.01
0.001
0.0001 0 20 40 60 80 100 120 140 160 180 200
Dark current [mV/s]
Figure 20. Cumulative Dark Current Distribution (in e/s) at 25 C Ambient Temperature
100 ext dev 1 ext dev 6 ext dev 10 int dev 1 int dev 6 int dev 10 average
10
Cumulative frequency
1
0.1
0.01
0.001
0.0001 0 2000 4000 6000 8000 10000 12000
Dark current [e/s]
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Figure 21 shows the percentage of pixels versus their normalized dark current for the measurement and for a Gaussian distribution with the same average value and standard deviation. In the measured distribution, about 1.1-1.2 % of the pixels exhibit a dark current that exceeds the 3 limit that is typically used to exclude pixels from the measurements (about 10 times larger than for Gaussian distribution). Figure 21. Comparison between Measured Distribution and Gaussian Distribution
100
measurement gaussian distribution
10
Percentage of pixels [%]
1
0.1
0.01
0.001
0.0001 0 1 2 3 4 5 6 7 8 9 10
(dark current - average dark current) / (st. dev. dark current)
Figure 22 shows the DSNU distributions during TID irradiation Figure 22. DSNU Distributions during TID Irradiation
DSNU distribution during Total Dose Irra diation and afte r annea ling
10000 Pre Rad 4Krad 14Krad 20Krad 41Krad 168h HT Annealing 3mnth RT Annealing Biased Conditions
Num ber of pix els
1000
100
10
1 0 500 1000 1500 2000 2500 3000 3500 4000 4500
A DU value [0 - 2^12 ]
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6.3.5 Temperature Sensor Figure 23. Temperature Sensor Voltage Sensitivity: The solid line indicates a linear fit with 1.38 V as output voltage at 30 C and a slope of -4.64 mV/C
1 .4 5
1.38
measurement points fitted curve deviation
4
1.36
3
1.32
1
1 .3
0
1.28
-1
1.26
-2
1.24
-3
1.22
-4
1 .2 30 35 40 45 50 55 60 65 70 75
-5
Temperature [C]
6.3.6 Pixel-to-Pixel Cross Talk Figure 24. Cross talk with central pixel uniformly illuminated with 100 %. Estimation from Knife-edge measurements
0.0 0.2 1.3 0.2 0.0
0.2 1.3 9.8 1.3 0.2
1.3 9.8 49.0 9.8 1.3
0.2 1.3 9.8 1.3 0.2
0.0 0.2 1.3 0.2 0.0
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Deviation from fitted curve [mV]
1.34
2
Output voltage [V]
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7. Pin Description
7.1 Pin Type Information
The following conventions are used in the pin list. Pin Types AI AO AB DI DO VDD GND Analogue Input Analogue Output Analogue Bias Digital Input Digital Output Supply Voltage Supply Ground
7.2 Power Supply Considerations
It is suggested to use one regulator for all digital supply pins together, one regulator for the sensor core analogue supplies together, and one regulator for the ADC analogue supply (if used). Analogue ground returns must be of very low impedance, as short-term peaks of 200mA can be encountered. The ADC can be disabled by connecting all of its power and ground pins to system ground, leaving all other pins open.
7.3 Pin List
Doubled-up pins have the same pin name, but are indicated with (*). These pins are at the same potential on the chip. Pin No. Name Type Power Supply and Ground Connections 10 33 11 32 8 35 9 34 55 73 58 70 74 VDD_DIG (1) VDD_DIG (2) GND_DIG (1) GND_DIG (2) VDD_ANA (1) VDD_ANA (2) GND_ANA (1) GND_ANA (2) GND_ANA (3) GND_ANA (4) VDD_PIX (1) VDD_PIX (2) VDD_RES VDD VDD GND GND VDD VDD GND GND GND GND VDD VDD VDD Reset power, 3.3V, optionally up to 5V for increased full well Sensor Biasing 75 52 51 GND_AB NBIAS_DEC NBIAS_PGA AB AB AB Antiblooming ground, connect to system ground or to a low-impedant 1V source for enhanced anti-blooming Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA Pixel array power, 3.3V Analogue ground Analogue power, 3.3V Logic ground Logic power, 3.3V Purpose
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Pin No. 50 49 48 47 46
Name NBIAS_UNI40 NBIAS_LOAD NBIAS_PRECHARGE NBIAS_PREBUF NBIAS_COLUMN
Type AB AB AB AB AB Connect to GND_ANA
Purpose Connect with 75k to VDD_ANA, decouple with 100nF to GND_ANA Connect with 110k to VDD_ANA, decouple with 100nF to GND_ANA Connect with 200k to VDD_ANA, decouple with 100nF to GND_ANA Connect with 110k to VDD_ANA, decouple with 100nF to GND_ANA
Analog Signal Input and Outputs 31 60 59 57 56 54 SIGNAL_OUT A_IN1 A_IN2 A_IN3 A_IN4 PHOTODIODE AO AI AI AI AI AO Output of PGA, range ## .. ## V, straight polarity i.e. a low output voltage corresponds to a dark pixel reading. Input to PGA input multiplexer. Input to PGA input multiplexer. Input to PGA input multiplexer. Input to PGA input multiplexer. Reference photodiode
Logic Control Inputs and Status Outputs 71 69 68 67 66 65 64 63 62 61 72 76 77 78 82 84 36 83 1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LD_Y LD_X LD_REG RES_REGn SYNC_YRD SYNC_YRST SYNC_XRD CLK_YRD CLK_YRST DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI DI Parallel sensor programming interface shared address/data bus, LSB Load strobe: copy A[9..0] into Y1 start register Load strobe: copy A[9..0] into X1 start register Load strobe: copy A[7..0] into parameter register indicated by A[9..8] Asynchronous reset for internal registers Initialise Y read shift register (YRD) to position indicated by Y1 start register Initialise Y reset shift register (YRST) to position indicated by Y1 start register Initialise X read shift register (XRD) to position indicated by X1 start register Advance shift register YRD one position Advance shift register YRST one position Parallel sensor programming interface shared address/data bus, MSB
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Pin No. 25 53 2 4 37 3 5 6 7 38 CLK_X EOS
Name
Type DI DO DI DI DI DI DI DI DI DI
Purpose Advance shift register XRD; note: two clock cycles needed for one pixel output End Of Scan monitor output for YRD,YRST,XRD shift registers, selected through an internal register Enable YRD to address the pixel array when `0'; Enable YRST to address the pixel array when `1' Reset the line pointed to by YRST (YRST_YRDn='1') or pointed to by YRD (YRST_YRDn='0') Assert when in line blanking / non-readout phase Select for readout the line pointed to by YRST (YRST_YRDn='1') or YRD (YRST_YRDn='0') Precharge column bus Sample the selected line's levels onto the column amplifier reset level bus Sample the selected line's levels onto the column amplifier signal level bus Calibrate PGA ADC
YRST_YRDn RESET BLANK SEL PRECHARGE R S CAL
30 27 23 22 21 20 19 18 17 16 15 14 13 12 43 42 41 44 45 39 40 81 80
IN_ADC CLK_ADC DATA_11 DATA_10 DATA_9 DATA_8 DATA_7 DATA_6 DATA_5 DATA_4 DATA_3 DATA_2 DATA_1 DATA_0 SPI_DIN SPI_LD SPI_CLK ADC_NBIAS ADC_PBIAS VLOW_ADC VHIGH_ADC REF_COMP_LOW REF_MID
AI DI DO DO DO DO DO DO DO DO DO DO DO DO DI DI DI AB AB AI AI AO AO
Analogue input to ADC ADC conversion clock, pixel rate, latency is 6.5 cycles ADC data output, MSB
ADC data output, LSB Serial calibration interface data in Serial calibration interface load strobe Serial calibration interface bit clock Connect with 60 kOhm resistor to ADC_PBIAS, decouple with 100nF to ground Connect with 60 kOhm resistor to ADC_NBIAS, decouple with 100nF to VDD_ADC_ANA ADC low threshold reference voltage, connect with 90 Ohm to GND and 130 Ohm to VHIGH_ADC, decouple with 100nF to ground ADC high threshold reference voltage, connect with 130 Ohm to VDD_ANA_ADC, decouple with 100nF to ground Decouple with 100nF to ground Decouple with 100nF to ground Page 41 of 71
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Pin No. 79 29 28 24 26
Name REF_COMP_HIGH VDD_ADC_ANA GND_ADC_ANA VDD_ADC_DIG GND_ADC_DIG
Type AO VDD GND VDD GND Analogue supply, 3.3V Analogue ground Digital supply, 3.3V Digital ground
Purpose Decouple with 100nF to ground
7.4 Electrical Characteristics
7.4.1 Multiplexer Inputs Pin nr. 60 59 57 56 7.4.2 Digital I/O Figure 25. Simulation results Digital "0" and Digital "1"
DC simulation of different input buffers of HAS2
3.50E+00
incertain if input is seen a s a high or lo w signa l
Name A_IN1 A_IN2 A_IN3 A_IN4
Imput impedance Capacitive 10pF Capacitive 10pF Capacitive 10pF Capacitive 10pF
Settling Time 100ns 100ns 100ns 100ns
3.00E+00
Lo w signa l
2.50E+00
L ow sign al, bu t le ackage curre nt thro ugh bu ffer
Output of buffert
2.00E+00
1.50E+00
High sign al, bu t le acka ge curre nt thro ugh buffer
1.00E+00
5.00E-01
High signal
0.00E+00 0.00E+00
5.00E-01
1.00E+00
1.50E+00
2.00E+00
2.50E+00
3.00E+00
3.50E+00
Digital input
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7.5 Package Pin Assignment
The HAS sensor is packaged in a 84 pins JLCC84 package with large cavity. The figure below shows the pin configuration. Figure 26. Pin Configuration
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 A0 A_IN1 A_IN2 VDD_PIX A_IN3 A_IN4 GND_ANA PHOTO_DIODE EOS NBIAS_DEC NBIAS_PGA NBIAS_UNI40 NBIAS_LOAD NBIAS_PRECHARGE NBIAS_PREBUF NBIAS_COLUMN ADC_PBIAS ADC_NBIAS SPI_DIN SPI_LD SPI_CLK VHIGH_ADC VLOW_ADC CAL BLANK SYNC_XRD VDD_ANA GND_ANA VDD_DIG
VDD_RES GND_ANA LD_Y A9 VDD_PIX A8 A7 A6 A5
A4 A3
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
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CLK_X GND_ADC_DIG CLK_ADC GND_ADC_ANA VDD_ADC_ANA IN_ADC SIGNAL_OUT GND_DIG
75 76 77 78 79 80 81 82 83 84 1 2 3 4 5 6 7 8 9 10 11
GND_AB LD_X LD_REG RES_REGn REF_COMP_HIGH REF_MID REF_COMP_LOW SYNC_YRD CLK_YRD SYNC_YRST CLK_YRST YRST_YRDn SEL RESET PRECHARGE R S VDD_ANA GND_ANA VDD_DIG GND_DIG
A2 A1
(0,1023)
(1023,1023)
Image Core 1024x1024
(0,0)
x- direction
(1023,0)
Drivers
ADC DATA<11> VDD_ADC_DIG
Output amplifier
53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
y-direction
DATA<9> DATA<10>
DATA<0> DATA<1> DATA<2> DATA<3> DATA<4> DATA<5> DATA<6> DATA<7> DATA<8>
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8. User Manual
8.1 Image Sensor Architecture
Sensor Block Diagram
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8.1.1 Pixel Architecture A square array contains 1024x1024 three-transistor linearly-integrating pixels of each 18 x 18 m. Each pixel has a connection for a reset line, for power, an output select line, and eventually the pixel's output signal Figure 27. Three-transistor Pixe: Transistor-level Diagram (left), and Functional Equivalent (right)
There are three transistors in a pixel. The first one acts as a switch between the power supply and the photodiode. The photodiode is equivalent to a capacitor with a light-controlled current source. The second transistor is a source follower amplifier, buffering the voltage at the photodiode/capacitor cathode for connection to the outside world. The third transistor again is a switch, connecting the output of the buffer amplifier to an output signal bus. Activating the reset line drains the charges present on the pixel's embedded photodiode capacitor, corresponding to a black, dark, pre-exposure state, or high voltage. As all pixels on a row (line) share their reset control lines, the pixels in a row can only be reset together. With both reset and select lines disabled the pixel amasses photo charges on its capacitor, charges generated in the photo-
diode by impinging photons. During this integration the voltage on the photodiode cathode decreases. When the select line is asserted the voltage on the capacitor is connected to the pixel output through the source follower buffer transistor. All pixels in a line have their select lines tied together: upon selection a whole line of pixel output signals is driven onto the 1024 column buses that lead into the column amplifiers for further processing and complete or partial sequential readout to the ADC. All pixels on a line have their reset lines tied together: the reset mechanism works on all pixels in a line simultaneously, no individual or addressed pixel reset (IPR) is possible.
Figure 28. Signal Lifetime in a Three-transistor Pixel: Reset to black level (high voltage), Photo Charge Integration (dropping voltage), voltage readout
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8.1.2 Array Coordinate System Figure 29. Front View of Sensor Die: Package pin 1 is on the left side. The focal plane origin is in the bottom-left corner. Lines (Y) are scanned down to top, pixels (X) left to right
8.1.3 Line Addressing The sensor operates line wise: a line of pixels can be selected and reset, and a line of pixels can be selected for readout into the column amplifier structures. There is no frame reset operation, there is no frame transfer. Image acquisition is done by sequencing over all lines of interest and applying the required reset and/or readout control to each line selected. The sensor array contains two vertical shift registers for line addressing. These registers are one-hot, i.e. they contain a pattern like "00001000000", at each time pointing to one line of pixels. Figure 30. Line Addressing Structures: YRD and YRST one-hot shift register pointers and Y1 programmable start-of-scan register
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In Double Sampling / Destructive readout, one of these registers is typically dedicated to addressing the lines to read, and the other is used for addressing the lines to reset as part of the electronic shutter operation. In Correlated Double Sampling / Non-Destructive Readout, it is the user's choice whether one or both shift registers will be used. Both Y shift registers can be initialized to a position indicated by an on-chip address register. This address register is written by the user through the parallel sensor programming interface. With this programmable initial position windowed readout (region-of-interest) is possible. Both registers can be advanced one position at a time under user control. 8.1.4 Pixel Addressing Pixels are read from left to right, generating a pixel-sequential output signal for each line. The pixel addressing is similar to the line addressing. Close to the column amplifiers resides a horizontal shift register for pixel/column addressing. This register is one-hot, i.e. it contains a pattern like "00001000000", at a time pointing to exactly one pixel and one column amplifier. Line acquisition is done by sequencing over all pixels of interest and applying each time the required pixel readout and ADC control signals. The X shift register can be initialized to a position indicated by an on-chip address register. This address register is written by the user through the parallel sensor programming interface. With this programmable initial position windowed readout (region-of-interest) is possible. The X register can be advanced one position under user control. This requires a pixel clock signal at twice the frequency of the desired pixel rate. 8.1.5 Column Amplifiers At the bottom of each column of pixels sits one column amplifier, for sampling the addressed pixel's signal and reset levels. These signals are then locally hold until that particular pixel is sent to the output channel, in this case PGA, multiplexer, buffer, and ADC. The combination of column amplifiers and PGA can perform Double Sampling: in this case a pixel's signal level is read into the structures, then the pixel is reset, then the reset level is read into the structures and subtracted from the previously-stored signal level, cancelling fixed pattern noise. In Correlated Double Sampling mode the column amplifiers are used in bypass mode, and the raw signal level (which can be either a dark reset level or a post-illumination signal level) is sent to the output amplifier, and then to the output for storage and correlated subtraction off-chip. This cancels fixed pattern noise as well as temporal KTC noise.
8.1.6 Input Signal Multiplexer An analogue signal multiplexer with six inputs connects a number of sources to the output buffer. One input always is connected to the pixel-serial output of the pixel array. Four inputs are connected to analogue input pins and are intended for monitoring voltages in the neighborhood of the sensor. The last multiplexer input is connected to the on-chip temperature sensor. The multiplexer is controlled by an internal register, written through the parallel sensor programming interface. 8.1.7 Programmable Gain Amplifier (PGA) A voltage amplifier conditions the output signal of the multiplexer for conversion by the ADC. Signal gain and offset can be controlled by a register written through the parallel sensor programming interface. When connected to the pixel array, the PGA also subtracts pixel black level from pixel signal level when in DS/DR mode. 8.1.8 Parallel Sensor Programming Interface The sensor is controlled via a number of on-chip settings registers for X and Y addressing, PGA gain and offset, one-off calibration of the column amplifiers, ... These registers are written by the user through a parallel bus. 8.1.9 12-bit Analog to Digital Convertor (ADC) The on-chip ADC is a 12 bit pipelined convertor. It has a latency of 6.5 pixel clock cycles, i.e. it samples the input on a rising clock edge, and outputs the converted signal 6 pixel clock periods afterwards on the falling edge. The ADC contains its own SPI serial interface for the optional upload of calibration settings, enhancing its performance. The ADC is electrically isolated from the actual sensor core: when unused it can be left non-powered for lower dissipation, and without risk for latch-up. When used, the input voltage range of the ADC is set with a two-node voltage divider connected to pins VLOW_ADC and VHIGH_ADC. The ADC has an accuracy of 10 bit at 5 Mhz operation speed. 8.1.10 Temperature Sensor A PN-junction type temperature sensor is integrated on the chip. The temperature-proportional voltage at its output can be routed to the ADC through one of the six analogue inputs of the multiplexer. The temperature sensor must be calibrated on a device-to-device base. Its nominal response is -4.64 mV/C .
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8.2 Image Sensor Operation
The following s describe the HAS' two readout mechanisms and give the detailed timing and control diagrams to implement these mechanisms. 8.2.1 Double Sampling - Destructive Readout In Double Sampling / Destructive Readout (DS/DR) mode the YRST pointer runs over the frame, top to bottom, each time resetting the line it addresses. Lagging behind this runs the YRD pointer, each time reading out the line it addresses. The distance between the YRD pointer and the YRD pointer is then propor-
tional to the exposure time, hence the electronic shutter operation. At line readout the signal levels of the pixels in the addressed line are copied onto the column amplifiers' signal sample nodes. Immediately after this the line of pixels is reset, and the pixels' black levels are copied onto the column amplifiers' reset sample nodes. This is destructive readout. The column amplifiers/PGA then subtract the black levels from the signal levels during sequential pixel out. This is uncorrelated double sampling, eliminating any static pixel-to-pixel offsets of the sensor array.
Figure 31. Double Sampling: Pixel signal is read (s), then pixel is reset, then reset level is read (r)
8.2.2 Correlated Double Sampling - Non-Destructive Readout In Correlated Double Sampling/Non-Destructive Readout (CDS/NDR) mode the YRST or YRD pointer quickly runs over the frame, top to bottom, resetting each line it addresses. This leaves the pixel array drained of charges, in black or dark state. Then the YRD or YRST pointer is run over the region of interest of the frame, and of each line addressed the pixels' black levels are read out and passed on to the ADC. The user stores these black levels in an off-chip frame-sized memory. Then the system is held idling during the exposure time. After the exposure time has elapsed, the frame is scanned once more with the YRD or YRST pointer, and each line addressed is read out again. These signal levels are passed on to the ADC and then to the end user. At the same time, the user retrieves the corresponding black levels from the memory and subtracts them from the signal levels. This is correlated double sampling, eliminating static offsets as well as kTC noise
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Figure 32. Correlated Double Sampling: Pixel is reset, reset level is read and stored (r), pixel is exposed, signal level is read (s), difference is output
8.2.3 Possible Exposure Times The range of exposure times attainable by the HAS is entirely dependent on the user control strategy, although two obvious scenarios can be envisaged: In Destructive Readout/Double Sampling, a typical case would be a minimal exposure time equal to the line readout time, and a maximal exposure time equal to the frame time. With 1024x1024 pixels in a frame, 10 frames per second, this amounts to 98s and 100ms. In Non-Destructive Readout/Correlated Double Sampling it is not even possible to pinpoint a typical case, as all depends on the exact reset (R), reset-read (r) and signal-read (s) scheme the user employs. In the specific case of 10MHz pixel rate rate operation, 10 windowed frames per second, and 40 windows of 20x20, each receiving the same exposure time, and the whole FPA reset (R) at the start of the frame, the minimal exposure time would be 7.3ms, the maximal exposure time 90.2ms. Depending on window configuration, shorter and longer times are possible, though. 8.2.4 Timing and Control Sequences Definitions The HAS is a line-scan imager with 1024 horizontal lines (Y) each of 1024 pixels (X). Pixel coordinates are defined relative to an origin (X=0,Y=0), and projected onto the user's display view: the origin (0,0) is in the top-left corner of the displayed image, lines are scanned top-down, and the pixels in a line are scanned left to right.
Windows or regions-of-interest are defined by their top-left and bottom-right coordinates (X1,Y1)-(X2,Y2). The full frame then corresponds to (0,0)-(1023,1023). Note that (X1,Y1) is to be programmed into the sensor, while (X2,Y2) is not: windowed readout is obtained by pointing the sensor to (X1,Y1), followed by reading out (Y2-Y1+1) lines of (X2-X1+1) pixels. A frame readout sequence consists of a number of line readout sequences. A line readout sequence consists of
A line select sequence for the YRD and YRST pointer shift registers, during which a line may be selected for readout and another line may be selected for reset A line blanking sequence during which the line selected for readout copies its pixel signals into the column amplifiers, the column amplifiers are operated, and both lines selected are optionally reset (the line selected for read can be reset as part of the destructive readout/double sampling operation; the other line can be reset as part of the electronic shutter operation). A pixel readout sequence
A pixel readout sequence consists of

Initialization of the pixel pointer XRD to position X1 A sequencing through the region-of-interest, While the output amplifier and the ADC are activated and pixel values are sequentially selected, connected to the PGA, and converted by the ADC.
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Figure 33. Line Selection Timing Diagram
Above timing diagram is valid for CLK_YRD/SYNC_YRD and for CLK_YRST/SYNC_YRST. Description t1 t2 t3 t4 t5 SYNC_Y* setup CLK_Y* high width CLK_Y* period Address delay Setup to next blanking 100 ns Min 50 ns 100 ns 200 ns 30 ns No constraint on duty cycle Typ Max Remarks
Destructive Readout Timing Diagram n this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the exposure time tEXP can be expressed as an equivalent number of lines. Table 16. Threads of Operation for Destructive Readout with Double Sampling Comment init expose .do nothing YRD - read side Load registers Y1 and X1 with the window start coordinates Initialize YRD with Y1 YRST - reset side Initialise YRST with Y1 For YRST = Y1 to Y1+tEXP loop .select line YRST .reset line YRST .wait for one line time .advance YRST one position end loop .select line YRST .reset line YRST .advance YRST
read
For YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for DS/DR .read pixels X1 to X2 .advance YRD end loop
Figure 34. DS/DR Sequence: Exposure is initiated with running YRST over the array, resetting lines. After tEXP YRD sTarts running over the array too, reading and then resetting lines
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Figure 35. Destructive Readout Timing Diagram
Description t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 YRST_YRDn setup YRST_YRDn hold BLANK hold BLANK hold CAL delay ref. BLANK R active when SEL RESET width S active when SEL BLANK setup S setup PRECHARGE width
Min 13 ns 10 ns 400 ns 30 ns 2s 11 ns 400 ns 100 ns 100 ns 2s 10 ns 100 ns 100 ns 22 ns 100 ns 25 ns
Typ 25 ns 25 ns 50 ns 25 ns
Max
Remarks
25 ns Second RESET is optional 25 ns When no second RESET Once per frame or per line
The CAL signal initiates the programmable gain amplifier to a known 'black' state. This initialization should be done at the start of each frame.
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Non-Destructive Readout Timing Diagram In describing this mode the unit of timing is conveniently chosen to equal the time needed to read out a line of pixels. Hence, the exposure time tEXP can be expressed as an equivalent number of lines. (Note however that the user is under no obligation to link tEXP to the line read time: tEXP can be chosen arbitrarily as its timing and nature are only dependent on the external system controlling the HAS). Table 17. Threads of Operation for Non-destructive Readout with Off-chip CDS Comment init YRD - read side Load registers Y1 and X1 with the window start coordinates initialize YRD with Y1 Initialize YRST with Y1 clear frame .do nothing for YRST = 1 to 1023 loop .select line YRST .reset line YRST .advance YRST one position end loop YRST - reset side
read black levels
for YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for CDS/NDR, black levels .read pixels X1 to X2 .advance YRD end loop wait for time tEXP for YRD = Y1 to Y2 loop .select line YRD .operate column amplifiers for CDS/NDR, signal levels .read pixels X1 to X2 .advance YRD end loop
exposure read signal levels
Proper operation can be attained by using just one Y pointer register, YRD or YRST, for all of the frame's phases. The above operation scheme is just an example, using YRST for the frame reset phase. Figure 36. CDS/NDR Sequence: First array is reset completely with YRST. Then black levels are read with YRD. Then, after a time tEXP, all signal levels are read, again with YRD
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Figure 37. Non-destructive Readout Timing Diagram
Description t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 SEL hold BLANK hold CAL delay ref. BLANK S/R active when SEL BLANK setup YRST_YRDn s/h RESET width BLANK setup S/R setup PRECHARGE width
Min 13 ns 100 ns 400 ns 13 ns 10 ns 400 ns 30 ns 2.4s 11 ns 11 ns 100 ns 25 ns
Typ 25 ns
Max
Remarks Optional, only when YRST is used instead of YRD
25 ns 25 ns 50 ns 25 ns 25 ns once per frame or per line/window
Figure 38. Pixel Readout Timing Diagram
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The externally applied clock CLK_X runs at twice the pixel rate. From address pointer XRD shift to output signal available exists a latency of 6 CLK_X cycles. The above timing diagram supposes an ADC sampling at the rising edge of CLK_ADC. Description t1 t2 t3 t4 CLK_X period output settle time output hold time CAL off setup 50 ns 2 ns BLANK off setup when no CAL Min 50 ns Typ 100 ns 15 ns Max Remarks 50% duty cycle required, +/-2.5 ns
PGA and Signal Multiplexer Control Figure 39. Programmable Gain Amplifier and Signal Multiplexer Diagram
Figure 40. Amplifier Calibration Timing Diagram
The output of the column amplifiers is a stream of raw or FPN-corrected pixels. These pixels then pass the Programmable Gain Amplifier, where gain and DC-offset can be adjusted. Then follows a signal multiplexer that selects between the pixel signal or the temperature sensor and four externally-accessible analogue inputs. The output of the multiplexer is buffered and then made available at output pad SIGNAL_OUT. The PGA must be calibrated periodically with a black reference input signal, triggered by CAL. After each change of the gain settings, the PGA have to be calibrated to set the correct offset on the PGA. It is suggested to make this CAL signal equal to the BLANK signal. Remark: The BLANK signal resets the X shift register. So after each active BLANK period, there has to be a SYNCING of the x shift register before reading out any pixel. For gain and offset control, see section 8.2.5 on page 56. Description t1 t2 CAL width CAL-to-pixel-readout Min 200 ns 50 ns Typ Max Remarks
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Multiplexer operation: MODE.PGA[2..0] 000 001 010 011 100 101 110 111 Changing gain during read out It's possible to change the gain settings during the read out of 1 line. The following procedure is suggested. For example: gain changing between pixel 56 and 57

Selected input pixel array TEMP AIN1 AIN2 AIN3 AIN4
When pixel 56 comes out, stop the x clock after the falling edge. The output stays at the same level of this pixel (see Figure 38 on page 53) Change the gain settings by setting the internal registers as described in section 8.2.5 on page 56 Assert the CAL signal for 200 ns but leave the BLANK signal inactive After the CAL signal has felled down, wait 50 ns. Reactivate the X clock starting with the rising edge The first pixel that comes out is pixel 57
The total time needed to change the gain settings is about 450 ns Hard Reset - Soft Reset - Hard-to-Soft Reset See "Reset Modes Timing Controls" on page 61. Figure 41. ADC Timing Diagram
The ADC is a pipelined device that samples on each rising edge of its clock CLK_ADC. The output DATA is updated on each falling edge of CLK_ADC. There is an input-to-output latency of 6.5 clock cycles. Description t1 t2 t3 t4 t5 input setup input hold sample clock Latency output delay Min 5 ns 20 ns 100 ns 6.5t3 10 ns 50% duty cycle required, +/-5% exact Typ Max Remarks
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8.2.5 Sensor Programming Parallel Sensor Programming Interface The operational modes and start-of-window addresses of the HAS are kept in seven on-chip registers. These internal registers are programmable through a parallel interface similar to the one on the STAR250. This interface comprises of a 10-bit wide A bus, and 3 load strobes: LD_X, LD_Y, and LD_REG. With LD_Y or LD_X asserted (rising edge), the full 10 bits of A are loaded into respectively the line start address (Y1) and the column start address (X1) (as similar to the STAR250). With a rising edge on LD_REG, the upper two bits of A are decoded as an internal register address, and the 8 lower bits of A are loaded into the corresponding register. These 4 registers are reset to their default values by asserting RES_REGn. Address Register Load Timing Diagram Figure 42. Line/column address upload timing diagram
The YRD/YRST and XRD pointer start address registers Y1 and X1 are latches that pass the input value when LD_Y/LD_X is asserted, and freeze their output values when LD_Y/LD_X is deasserted
Description t1 t2 t3 t4 A setup LD_* width delay A hold
Min 100 ns 100 ns 75 ns 100 ns
Typ
Max
Remarks
Figure 43. Mode Registers Upload Timing Diagram
The mode setting registers are edge-triggered flip flops that freeze their outputs at the rising edge of LD_REG. Description t1 t2 t3 t4 A setup LD_REG width delay A hold Min 100 ns 100 ns 75 ns 100 ns Typ Max Remarks
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Internal Registers Global Description Are registers are programmed using the parallel upload interface. Two styles of register access methods are used. Address registers loaded with LD_Y or LD_X: Register name Y1 X1 Value A[9..0] 9:0 9:0 Default 0 0 Description start position of the YRD and YRST one-hot addressing shift registers, range 0..1023 start position of the XRD one-hot pixel address register, range 0..1023
Mode registers loaded with LD_REG and reset to default with RES_REGn: Register name MODE Address A[9..8] 00 Value A[7..0] 6:5 4:2 1 0 AMP BLACK OFFSET 01 10 11 7:2 1:0 7:0 7:0 Default 0 0 0 0 0 0 0 0 Description End of scan multiplexer PGA input multiplexer 1 = non destructive readout 0 = destructive readout, dual sampling 1 = standby 0 = APS in active mode Amplifier raw offset Amplifier gain. NDR mode black level DR mode column bus offset correction
Internal Registers Detailed Description X1 Register: X1 A[9..0] = X1[9..0] X1[9..0] Y1 Register: Y1 A[9..0] = Y1[9..0] Y1[9..0] start coordinate of YRD and YRST shift registers for line scan strobe :LD_Y start coordinate of XRD shift register for pixel scan strobe: LD_X
Legal (decimal) values are 0 (first line of the array) to 1023 (last line of the array) MODE Register: MODE A[9..8] = "00" LD_REG
A[7..0] = "X"&EOS[2..0]&PGA[2..0]&NDR&StandBy EOS[1..0] 00 01 10 11 PGA[2..0] Document Number: 001-54123 Rev. *A End-Of-Scan indicator selector output of YRD shift pointer register to pin EOS output of YRST shift pointer register to pin EOS output of XRD shift pointer register to pin EOS output of XRD shift pointer register to pin EOS PGA input multiplexer Page 57 of 71
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MODE
A[9..8] = "00" 000 001 010 011 100 101 110 111 pixel array TEMP temperature sensor AIN1 analogue telesense input AIN2 AIN3 AIN4
LD_REG
NDR 0 1 StandBy 0 1
Non-Destructive Readout selector NDR off, DS/DR enabled NDR on, CDS/NDR enabled power switch sensor operational sensor in standby / low power NDR selects DR or NDR mode. Standby puts the sensor in a low-power mode, in which the current mirror bias network drivers of the column structures, PGA, output buffer, and internal offset DACs are disabled. LD_REG
EOS[1..0] connects the output of the last stage of either one of the internal array=addressing shift register pointers YRD, YRST or XRD to the outside world at pin EOS. PGA[2..0] selects one of 6 possible analogue signals to be connected to the analogue output pin. AMP A[9..8] = "01"
A[7..0] = Offset[5..0]&Gain[1..0] Offset[5..0] Gain[1..0] 00 01 10 11 PGA offset PGA gain 1 2 4 8 The reset value of AMP.Offset is 0, decoding to the middle offset value of 0.8V. AMP.Offset range 0 to 31 corresponds to levels of 0.8 to 1.3V, while AMP.Offset range 32 to 63 corresponds to levels of 0.3 to 0.8V. Gain is controlled in 4 steps for nominal values of 1,2,4, and 8. Real gain values are expected to be somewhat lower and will be characterized.
This register sets the Programmable Gain Amplifier's output offset and gain. The PGA output signal offset is controlled in 64 steps of 16 mV each, from 0.3 V to 1.3 V. Output offset control is used to adapt the PGA's output to the ADC used (internal or external ADC). See "Other definitions:" on page 3. For unity gain and internal ADC use, the recommended default setting is: AMP_OFFSET = 60
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BLACK Register: BLACK A[7..0] = BLACK[7..0] BLACK[7..0] NDR mode black level 2.9V in steps of 10mV. BLACK range 128 to 255 corresponds to 0.4V to 1.65V in steps of 10 mV. The recommended default setting is: BLACK = 10 A[9..8] = "10" LD_REG
The BLACK register sets the black level of the column amplifier structures and column prechargers when used in NDR mode. The reset value of BLACK is 0, setting the internal black level to half-way full scale: BLACK range 0..127 corresponds to 1.65V to OFFSET Register: OFFSET A[7..0] = OFFSET[7..0] OFFSET[7..0] A[9..8] = "11"
LD_REG
Column bus offset correction.
The column signal path and later parts of the signal path is split in an odd bus with amplifiers and an even bus with amplifiers. Using the OFFSET register, the offsets for these two signal paths can be calibrated to obtain a balanced performance. The reset value of OFFSET is 0, driving the offset generator to half-scale (0mV) . OFFSET range 0 to 127 corresponds to 0 to +17.5mV in steps of 140V. OFFSET range 128 to 255 corresponds to -17.5mV to 0mV in steps of 137V. Expressed in electrons, this gives the following numbers: Total offset correction range: 2365 electrons Step of correction: 9.3 electrons The recommended default setting is: OFFSET = 0 (sample depended). It's recommended to calibrate the device while taking a dark image. 8.2.6 Sensor Calibration NDR Mode Black Level BLACK=10. Column Amplifier Offset Correction The column amplifier structures comprise of two independent signal buses, one handling pixels from odd columns, one handling pixels from even columns. ADC Serial Interface
As these structures are inherently imperfectly matched in offset, user calibration of this parameter is required when the sensor is operated in destructive readout / double sampling mode. The default (reset) values for this parameter puts the internal calibration signal generators in their neutral, middle-value mode. ADC Corrections Concept The ADC is a pipelined device with 11 identical conversion stages in series. Each conversion stage is built around an amplifier with calibratable gain. Each amplifier's gain can be tuned individually with an 8 bit code, totaling 11 words of 8 bits to be loaded into the ADC through a separate serial interface. ADC Tuning Codes Tuning codes each span the range 0 to 255, with value 127 denoting the amplifier's central gain setting (default after power-on, i.e. without user calibration, and allowing nominal operation of the device). Code 0 reduces the gain with 5%, tuning code 255 increases gain with 5%. The code-gain relation is guaranteed monotonous. ADC Linearity Tuning Method The ideal calibration code is 75 for each stage. It is expected that a complete set of calibration values will be provided in the sensor datasheet, or when necessary, with each device individually.
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Description t1 t2 t3 SPI_CLK width SPI_LD setup SPI_LD width
Min 1000 ns 0 ns 1000 ns
Typ
Max
Remarks
All 11 8-bit correction words are uploaded in one burst of 88 bits. The word for stage 11 first, then stage 10, and so down to stage 1. Within each word the MSB comes first. Bits are sampled on the rising edge of SPI_CLK, and thus should change on the falling edge of SPI_CLK. The complete set of words is registered in the ADC on the rising edge of SPI_LD. 8.2.7 Sensor Biasing The operating points of the sensor and ADC's analogue circuitry are set with external passive components (resistors and capacitors). These components have their recommended values listed in "Detailed Information" on page 3 (pin list). ADC Input Range Setting The input voltage range of the ADC (pin ADC_IN) is to be matched to the signal at hand, in this case the output voltage range at pin SIGNAL_OUT.
The lower threshold is set to the voltage injected at pin VLOW_ADC. The upper threshold is set to the voltage injected at pin VHIGH_ADC. For both settings it is recommended to use a resistive voltage divider: 90 Ohm from GND_ADC_ANA to VLOW_ADC, 130 Ohm from VLOW_ADC to VHIGH_ADC, 130 Ohm from VHIGH_ADC to VDD_ADC_ANA. 8.2.8 Temperature Sensor An internal temperature sensor presents a temperature-dependent voltage which can be made available at pin SIGNAL_OUT through the multiplexer. The voltage-temperature dependency is approximately -4.64 mV/C, but the absolute level is to be characterized on a device-by-device basis for demanding applications. With the on-chip ADC biased for an input window of 0.7 to 1.9 V, the temperature sensor/ADC combination can be used from -40 to +125 C.
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8.2.9 Reset Modes Timing Controls Figure 44. Hard Reset
Figure 45. Soft Reset
Figure 46. Hard to Soft Reset
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8.3 Application and Test Circuits
Figure 47. Sensor Pinning
All ground pins may be connected to 1 point except the anti blooming ground (GNDAB).
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Figure 48. Sensor Biasing Circuits
Figure 49. Sensor Power Supply Decoupling Circuits
Figure 50. Reference Voltages End Circuit
Figure 51. Sencor ADC Circuitry
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The reference voltages can be either injected by a power supply voltage or can be generated from a resistance divider. See "ADC Input Range Setting" on page 60.
8.4 Device handling
8.4.1 Handling Precautions The component is susceptible to damage by electro-static discharge. Therefore, suitable precautions shall be employed for protection during all phases of manufacture, testing, packaging, shipment and any handling.
Until proven otherwise by evaluation testing these devices must be considered as Class 0 in the HBM ESDS component classification. This specification can possibly be widened when the results of the evaluation test program are known. 8.4.2 Storage Information The components must be stored in a dust-free and temperature-, humidity and ESD controlled environment. The specific storage conditions are mentioned in Table 2 on page 9 of this specification.
9. Frequent Asked Questions
Question: In my datasheet for the HAS2, the pixel readout timing diagram is lacking some information I need. It appears SYNC_X should change on the rising edge of CLK_X. And while SYNC_X is high, a rising edge of CLK_X should sync XRD to X1 register. But the diagram shows SYNC_X high for 2 CLK_X periods. Due to timing variations, SYNC_X could technically be high for as many as 3 different rising edges of CLK_X! The timing diagram doesn't show any setup or hold timing for SYNC_X and CLK_X. Answer:
CLK_X is divided internally in the sensor. SYNC_X is based upon this divided clock. When SYNC_X is high for a even pair of this divided clock cycles the XRD will be pushed the length of this even pair of clock cycles. Though, when SYNC_X drops during an un-even pair of divided clock cycles it is unclear what XRD will do. But this behavior is most unlikely. Question: RES_REGn doesn't have any timing info either. It's the asynchronous reset for internal registers. How long must it be held low? Answer: To be on the safe side you have to keep it low for at least 1us. You can apply the following sequence when powering up the sensor:

Power on device with known register settings During power on, keep RES_REGn low for at least 1us Apply Line/column address upload timing diagram
Question: The ADC serial interface timing diagram is incomplete. It appears the SPI_DATA is supposed to change on the falling edge of SPI_CLK. If so, then what is the setup and hold times of the SPI_DATA around the rising edge of SPI_CLK? The SPI_CLK has a period of 1000 ns, so the SPI_DATA would be present for 500 ns prior to the rising edge of SPI_CLK. But what is the SPI_DATA setup time for the *first* rising edge of SPI_CLK (first bit of data)? Answer: The best way to operate the device is to change your SPI data during the falling edge of the SPI clock. This gives you plenty of time before the data is being sampled on the rising edge of the SPI clock. Document Number: 001-54123 Rev. *A Page 64 of 71
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But to answer onto the question. You have to consider a 100ns hold and setup time of the SPI data around the rising edge of the SPI clock. Theoretically you are right about the 500ns but please consider 100ns for your timing. For the first rising edge please consider a 500ns setup time for the SPI data. Question: I noticed that BLANK remains high for the Destructive readout timing diagram, and even during the reset of YRST row. But in the Nondestructive readout timing diagram, you have BLANK shown going low between a reset and line selection, but no timing information regarding that. What does the timing need to be? Or can I leave BLANK constantly high during a line reset and subsequent line selection during Nondestructive readout? Answer: For the non destructive read out you can extend T1 and reduce T4. So meaning that you can leave the BLANK signal high.
Question: What is your recommendation to do with the unused Analog inputs to the multiplexor (A_IN1-4)? Grounding them would place them at 0 volts which is outside of the VLOW_ADC range. Should they be left floating? Or should they be tied to some constant voltage source between VHIGH_ADC and VLOW_ADC? Answer: If you don't use the analog inputs I propose to ground them. But most of our customers are using these inputs to monitor some supply voltages. For example, you could monitor your 3.3V input voltage. Of course you have to divide it with a resistance divider to have the voltage inside the ADC range. You could use it also to monitor some external voltages that are used on your board and which are important to be stable. Just some idea's... Question: What are the implications of turning off the analog power supplies (VDDA), but keeping the digital power supply (VDD) active? Is this bad? I'm trying to improve the standby low power mode. Answer: No this is not bad. In fact the total power supply current will reduce even a little bit more. Question: Spec sheet describes the ADC input range setting: 90 Ohm from GND_ADC_ANA to VLOW_ADC, 130 Ohm from VLOW_ADC to VHIGH_ADC, 130 Ohm from VHIGH_ADC to VDD_ADC_ANA. The VDD_ADC_ANA is 3.3V so this puts VLOW_ADC = 0.85 V and VHIGH_ADC = 2.07 V. But Table 14 on page 24 lists typical power supply settings and sensor settings: It says ADC_VLOW = 0.8V and ADC_VHIGH = 2.5V. Which way do you recommend? Can you describe the discrepancy? Answer: The correct ADC range is as you described with the resistance divider. An alternative without resistance divider is to directly inject this voltage by a power supply circuitry. This how we do it inside our characterization system. In that way you can tune your ADC settings as you want. But if you want to stick with the resistances please use the values as described above. Table 14 on page 24 is a typo. It should be 0.85V and 2.0V Document Number: 001-54123 Rev. *A Page 65 of 71
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Question: In your datasheet, ADC High/Low bias voltages are recommended to be set with a resistive divider. But the datasheet doesn't mention anything about temperature stability. For the STAR-1000, there was an internal resistor between ADC_HIGH and ADC_LOW that had temperature dependence. Because of this, for STAR-1000 designs, I used to set my ADC bias voltages with buffers that would keep the bias levels constant over temperature. Do I need to repeat the same principle for the HAS2? Or does the HAS2 remove any temperature dependence for the ADC bias voltages? Answer: For good temperature stability, it is better the same principle as the STAR-1000. So use external buffers to keep ADC_HIGH and ADC_LOW to a fixed voltage level Question: In your datasheet, in the "ADC Timing Diagram" on page 55, the table lists t5, output delay, as typically 10 ns. The STAR-1000 had a troublesome output delay variability of 20 - 60 ns, some parts had even 70 ns! Have the digital output drivers been significantly improved for the HAS2 ADC? What are typical rise/fall times for the outputs? Answer: The output delay and stability has been improved compared to STAR-1000 Question: Could you please discuss the differences between BLANK, CAL, and PRECHARGE? The STAR-1000 only had a CAL signal. Answer: The extra BLANK signal is used to reset the internal CLKX divider. PRECHARGE is used to pre-charge the column lines and column caps to ground Question: I liked the flexibility of the STAR-1000. The HAS2 seems more restrictive. For example, your application note says, "...repeated use of pixel re-addressing (register X1) potentially injects offset-noise into any windows that overlap in Y-coordinates." If I understand correctly, this means I cannot address each pixel along a line individually? I cannot readout every other pixel, or every 2nd, or 5th, or 10th? I have to readout all the pixels in a line? Can you think of any options? Answer: You still can start reading at any X or Y position. You have only keep in mind that there is an analog pipeline on the pixel data. So if you individual read 2 pixels of the same line closer together then the analog pipe, the second pixel will be addressed when you are only interested in the first pixel. So when you want to read that second pixel by a new SyncX, it will be the second time you address it. As a result, there is a risk of a deviated value. Probably some deviated offset on the pixel value. You have probably the same problem with STAR-1000 but maybe the analog pipe is there smaller. Question: For NDR/CDS mode, there is parasitic exposure given your suggested algorithm. Can I do this algorithm instead? a. Reset Row X i. Start integration timer b. Readout Row X c. Reset Row X+1 d. Readout Row X+1 e. Reset Row X+2 f. Readout Row X+2 g. (repeat to region of interest) h. (wait for integration timer completion) i. Readout Row X j. (wait for time to reset a row) k. Readout Row X+1 l. (wait for time to reset a row) m.Readout Row X+2 n. (wait for time to reset a row) o. (repeat to region of interest) Answer: I don't see a problem with your algorithm
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Question: I would be interested to get more insight about the HAS anti-blooming capability. In our target application, we must be able to operate with the sun in our field of view. From initial calculations, this means that we can have a sun spot on the sensor around 50 pxls in diameter, over-exposed by a factor of ~1000 against our other target spots.My questions are :

What is the role of the anti-blooming ground pin (GND_AB) and how does it impact the sensor behavior? Is the anti-blooming capability sufficient to prevent any additional "recovery" time of the sensor? What pixel to pixel crosstalk behavior can we expect around the sun spot? 9.8% of the full well ( Table 13 on page 24), or ...
Answer: When a pixel is saturated and even goes to negative voltage levels, it isn't anymore suitable for lower electro potential level to attract new photon-electrons. So the extra photo-electrons can now more easily go to nearby pixels instead of to the pixel where the electrons are generated. This is visible in the image as blooming. The anti-blooming method is keeping the photo-diode at an attractive electro-potential that still attract new electrons. This can be done by holding the gate of the reset transistor higher then ground level. The 'row_select' line thats selects a specific row of the pixel array is a digital signal that swaps between 'GND_DIG' and 'VDD_DIG'. The 'row_reset' line that resets a specific row of pixels uses the same drivers as the 'row_select' line but the lower voltage level isn't 'GND_DIG' but 'GND_AB'. So the lower level of gate of the pixel reset transistor can be set by adapting the voltage level of 'GND_AB'. It is suggested to not go higher with the voltage level of 'GND_AB' than 1V. The digital circuits of the sensor should still see it as a digital '0'. Some second order effect of keeping GND_AB higher then ground:
The swing of row_reset is now lower. This means less cross-talk to the photo-diode and higher dark-level. Probably you don't see much changes if you read the sensor in dual sampling. Both the signal and the dark reference changes in level, so the subtraction is still the same. But you use the photo-diode on a slightly higher voltage level. Therefore, the pixel cap can be a little lower. (Non linear behavior of the cap of a diode). The swing of the diode is also lowered, but probably only the part of the swing that was not read-out anyway.
It is very difficult to get any quantification of the anti-blooming effect. The best way of figuring is just trying it. The anti-blooming function is not part of the characterization of the sensor.
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Question: I am trying to estimate the pulse height distribution (PHD) from electrons and protons traversing the focal plane array. The PHD is the probability of seeing a pulse of a given size in a single pixel from an electron or proton coming from a random direction and striking in a random location. When an electron traverses a unit cell it excites electrons. The total amount of charge is proportional to the length of the path (the chord length) through the unit cell. Charge that is created outside the collection region of the detector has little effect. The charge in the photodiode is collected and looks like signal. In order to calculate the chord length distribution through the photodiode I need its dimensions. I have been assuming that it is 7.5 microns on a side, living within the 15 micron unit cell. The thing I have no clue about is the thickness of the collection region. It could be quite thick, but I have been assuming a fairly thin geometry. The production of streaks by protons is sensitive to the thickness of the photodiode as well (thicker means longer streaks). >So I think the answer to your question is that I need all three dimensions of the photodiodes in the array. I would also like to know if the unit cells are simply repeated across the array or if they are arranged with mirror images next to each other (or something like that) which would make the light sensitive regions cluster in groups of two or four. Answer:
Question: Will pixel-to-pixel crosstalk only appear if a pixel is fully saturated? Or will it also appear if for instance the pixel is only as half it's full well capacity. If it does happen even if the pixel is not fully saturated do you know to what extent it will happen - will it also be the same extent as shown in "Pixel-to-Pixel Cross Talk" on page 38 of your datasheet? Will pixel-to-pixel crosstalk only lead to charge leaking from a pixel with higher signal to a pixel with low signal or vice versa?
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Answer: The pixel-to-pixel crosstalk chown in "Pixel-to-Pixel Cross Talk" on page 38. is cross-talk caused by floating generated electrons that are not yet captured by any photo-diode. So it has nothing to do with the actual level on the accumulated photo-diodes. Only when the photo-diode is really totally saturated, the floating electrons can behave differently. The saturated photo-diode cannot capture more electrons, so incoming electrons are not kept. The generated electrons will be captured by neighboring photo-diodes that are not yet completely saturated (or recombined). So cross-talk as measured in "Pixel-to-Pixel Cross Talk" on page 38 goes both from pixel with higher to lower signal levels and vice versa. It doesn't matter as long they are not fully saturated. Note that the anti-blooming ground can keep the pixel out of a completely saturation state. Question: The test results after proton beam are not as expected. In order to interpret the results we want to know what the thickness is of the epitaxial layer. Ore more in detail the thickness of the active area of the photo diode. Answer: EPI thickness: 5m, the nwell is about 1um deep. Question: How large is the active area compared to the overall pixel? Almost the whole photo-sensitive area is active area. Answer: 96% of the whole pixel is active area. Everything expect the transistors and nwell, is p-doped Question: Is there a spice model available for the radiation hard pixel used in the HAS device? Answer: No. The models that are used are just non-radiation hard models. Question: What is the penetration depth of photons in the HAS2 pixel versus the spectral range? Doe we have such graphs available? Answer: This is theory. We have penetration versus spectral range but this depends on the actual doping levels of the substrate. So it is never actual measured. Question: How would the MTF behave with increasing wavelength? Is there an MTF graph available versus spectral range? Answer: You can expect a large decrease in MTF when using higher wavelengths. To known how it behaves on the HAS2, new MTF measurements are needed. Question: In chapter 6.2 of the actual data sheet it is suggested to use one regulator for all digital supply pins together, one regulator for the sensor core analogue supplies together, and one regulator for the ADC analogue supply. Against it the test circuit in chapter 7.3 uses 5 different supply voltages (VDDD, VDDA, VPIX, VadcA, VadcD). With the first information I decided to use 3 regulators: One for VDD_ANA + VDD_PIX, one for VDD_DIG + VDD_ADC_DIG and one only for VDD_ADC_ANA. Moreover I use two grounds (analog and digital). Sadly with this configuration I have some problems in Window-Mode. Every 2nd line of the first lines of a window overshoot there. The more lines are sampled the lower is that effect. After may be 20 to 30 lines the effect exists no longer. In an other PCB I use a separate regulator for VDD_PIX instead for VDD_ADC_ANA (VDD_ADC_ANA is connected to VDD_ANA) and everything works fine. Could that may be the problem or do you have any other ideas? Answer: I expect that the peak currents of VPIX make the power regulator that you use unstable. This is no problem as long the VPIX isn't use by other parts of the sensor. So it is normal that when VPIX has its own regulator, nothing strange becomes visible in the image. But probably, VPIX is still not stable. However, the double sampling (both the signal and the black level are affected by the voltage level of VPIX) hide the problem for you.
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10. Addenda
AN-APS-FF-WO-06-001 (v1.): Application note on HAS readout methods
11. Optical quality - Definitions
The following definitions and limits are used to define the optical quality of the HAS2 type variants as outlined in Table 1 on page 8 of Section "Specification Tables" on page 8. Dead Pixel A dead pixel is defined as a pixel which has no electrical response. In the image this is resulted in a pixel with fixed ADC value. The number of pixels with ADC value 0 are count and accumulated. Bright Pixel in FPN image A FPN image is defined as a dark image with the shortest possible integration time. A bright pixel in this image is defined as a pixel with an ADC value higher then 20% of the full range of the entire pixel array. Bad Pixel in PRNU image A PRNU image is defined as an image where all pixels have a 50% response of the full range of the entire pixel array. A bad pixel in this image is defined as a pixel with an ADC value that differs more then 10% of the average response. This average reponse can be calculated on the total pixel array for a global measurement or on 32x32 pixels for a local measurement. Bad Row/Column A bad row/column is detected in the PRNU image. A row / column is defective when it differs more then 5% from the average of a moving window of 32 rows/columns. A row/column is also defined as defective when it has 100 or more adjacent bad, bright or dead pixels.
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CYIH1SM1000AA-HHCS
Document History Page
Document Title: CYIH1SM1000AA-HHCS Detailed Specification - ICD Document Number: 001-54123 Revision ** *A ECN 2725727 2765859 Orig. of Submission Change Date FVD NVEA See ECN 09/18/09 Initial Release Updated Ordering Information table Description of Change
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54123 Rev. *A
Revised September 18, 2009
Page 71 of 71
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